p p js 64 16 december 31 ,2014 - rev.0 2 page 1 2 0 v n - c hannel enhancement mode mosfet voltage 2 0 v current 7.4 a sot - 23 6l - 1 unit : inch(mm) f eatures ? r ds(on) , v gs @ 4.5 v , i d @ 7.4 a< 2 7 m ? ? r ds(on) , v gs @ 2 .5 v , i d @ 4.7 a< 4 1 m ? ? r ds(on) , v gs @ 1 .8 v , i d @ 1.8 a < 85 m ? ? advanced trench process technology ? specially designed for switch load, pwm application, etc. . ? lead free in compliance wit h eu rohs 2011/65/eu directive . ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: sot - 23 6l - 1 package ? terminals: solderable per mil - std - 750, method 2026 ? approx. weight: 0.0005 ounces, 0.014 grams ? marking: s 16 parameter symbol limit units drain - source voltage v ds 20 v gate - source voltage v gs + 12 v continuous drain current i d 7 . 4 a pulsed drain current i dm 29.6 a power dissipation t a =25 o c p d 2 w derate above 25 o c 1 6 m w/ o c operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal resistance - j unction to ambient (note 3 ) r ja 62.5 o c /w maximum ratings and thermal characteristics (t a =25 o c unless otherwise noted)
p p js 64 16 december 31 ,2014 - rev.0 2 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs = 0 v, i d = 25 0ua 2 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = 250 ua 0.5 0.7 7 1.2 v drain - source on - state resistance r ds(on) v gs = 4.5 v, i d = 7.4 a - 2 4 2 7 m gs = 2.5 v, i d = 4.7 a - 3 3 4 1 v gs = 1.8 v, i d = 1.8 a - 6 2 8 5 zero gate voltage drain cu rrent i dss v ds = 20 v, v gs =0v - 0.01 1 u a gate - source leakage current i gss v gs = + 12 v, v ds =0v - + 10 + 10 0 n a dynamic total gate charge q g v ds = 10 v, i d = 7.4 a, v gs = 4.5v (note 1 , 2 ) - 6. 8 - nc gate - source charge q gs - 1.3 - gate - drain charge q gd - 2 - input capacitance ciss v ds = 10 v, v gs = 0 v, f=1.0mhz - 513 - pf output capacitance coss - 74 - reverse transfer capacitance crss - 60 - switching turn - on delay time t d (on) v dd = 10 v, i d = 7.4 a, v g s = 4.5v, r g = 6 (note 1 , 2 ) - 7 - ns turn - on rise time tr - 5 7 - turn - o ff delay time t d (off) - 2 4 - turn - o ff fall time tf - 1 4 - drain - source diode maximum continuous drain - source diode forward current i s --- - - 2.0 a diode forward voltage v sd i s = 1.0 a, v gs = 0 v - 0. 69 1. 2 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined a s the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper 4. the maximum current rating is package limited
p p js 64 16 december 31 ,2014 - rev.0 2 page 3 t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characterist ics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode characteristics
p p js 64 16 december 31 ,2014 - rev.0 2 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 capacitance vs. drain - source voltage .
p p js 64 16 december 31 ,2014 - rev.0 2 page 5 part no packing code version mounting pad layout part no packing code package type packing type marking ver sion pjs64 16 _ s 1_00001 sot - 23 6l - 1 3k pcs / 7
p p js 64 16 december 31 ,2014 - rev.0 2 page 6 disclaimer
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